virtio-comment

The spec says (v1.1 4.1.4.5 ISR status capability):

The VIRTIO_PCI_CAP_ISR_CFG capability refers to at least a single byte, which contains the 8­bit ISR
status field to be used for INT#x interrupt handling.

and

to avoid an extra access, simply reading this register resets it to 0 and causes the device to de­assert the
interrupt.
In this way, driver read of ISR status causes the device to de­assert an interrupt.

See sections 4.1.5.3 and 4.1.5.4 for how this is used.

and in 4.1.5.4 Notification of Device Configuration Changes

it says:

• If MSI­X capability is disabled:
1. Set the second lower bit of the ISR Status field for the device.
2. Send the appropriate PCI interrupt for the device.

If MSI­X capability is enabled:
1. If config_msix_vector is not NO_VECTOR, request the appropriate MSI­X interrupt message for
the device, config_msix_vector sets the MSI­X Table entry number.

all of the above make it looks like VIRTIO_PCI_CAP_ISR_CFG capability is
unused with MSIX.

This was actually the way the spec was understood by
Zhu Lingshan from Intel (Cc'd).

However, looking at the conformance statements, one finds out this is
not the case:

4.1.4.5.1 Device Requirements: ISR status capability


The device MUST present at least one VIRTIO_PCI_CAP_ISR_CFG capability.
The device MUST set the Device Configuration Interrupt bit in ISR status before sending a device configu­
ration change notification to the driver.
If MSI­X capability is disabled, the device MUST set the Queue Interrupt bit in ISR status before sending a
virtqueue notification to the driver.

which implies that the Device Configuration Interrupt bit is set unconditionally.



It is unfortunate that it does not copy this requirement in more places,
and that the non-conformance text is incomplete and does not
mention the MSI-X usage at all.

I propose to extend 4.1.4.5 ISR status capability and
4.1.5.4 Notification of Device Configuration Changes
to mention the MSI use.

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MST