Adding background to Tiwei's comments on reason why tail pointer is good for hardware implementation:
Assuming no tail pointer:
1. Hardware would have to speculatively read descriptors and check their validity by checking that DESC_HW=1.
1.1 Yes Hardware could request a large number of descriptors at a time, making the pcie read response transfer (i.e. read descriptors) an efficient PCIe transfer.
The problems are as follows:
2. Issue 1: Wasting PCIe bandwidth
2.1 Although the PCIe read responses may be efficient transfers, if they contain invalid descriptors (DESC_HW=0), we have wasted PCIe bandwidth. This can be a problem when trying to maximize the performance possible from a design.
3. Issue 2: Wasting Hardware memory resources
3.1 When issuing PCie read requests for descriptors, the hardware must reserve inadvance memory to store the descriptors.
3.2. Given PCIe read latencies can be in the order of 1us, this memory is reserved for that length of time.
3.3. For hardware, 1us is a very long time and for FPGAs, memory is not as plentiful/cheap as in a PC.
3.4 So reserving memory for descriptors that may end up being invalid is a waste. Ultimately, this could effect performance if a large number of invalid descriptors are being read.
So it is better for hardware to know which queues (and hence guests) have descriptors available and fetch those only.
The argument above is biased towards Tx (transfer of packets from guest to device) but does also apply for Rx.
Tail pointer resides in the hardware and so the hardware always knows how many descriptors are available for each queue (no need to waste PCIe bandwidth to determine this) and so can fetch only those valid descriptors.
Regards
Kully