make it all LE and require natural width accesses resolves VIRTIO-9 Signed-off-by: Michael S. Tsirkin <
mst@redhat.com> --- virtio-v1.0-wd01-part1-specification.txt 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/virtio-v1.0-wd01-part1-specification.txt b/virtio-v1.0-wd01-part1-specification.txt index 91ee13e..d9a6de7 100644 --- a/virtio-v1.0-wd01-part1-specification.txt +++ b/virtio-v1.0-wd01-part1-specification.txt @@ -88,6 +88,8 @@ o Feature bits o Configuration space o One or more virtqueues +Unless explicitly specified otherwise, all multi-byte fields are little-endian. + 2.1.1. Device Status Field ------------------------- @@ -202,7 +204,13 @@ Interface' in the section title. Configuration space is generally used for rarely-changing or initialization-time parameters. -Note that this space is generally the guest's native endian, +Note that configuration space generally uses the little-endian format +for multi-byte fields. + +100.100.4.1. Legacy Interface: A Note on Configuration Space endian-ness +-------------------------------------- + +Note that for legacy interfaces, configuration space is generally the guest's native endian, rather than PCI's little-endian. 2.1.4. Virtqueues @@ -689,13 +697,14 @@ device-specific region. There may be different widths of accesses to the I/O region; the “natural” access method for each field in the virtio header must be -used (i.e. 32-bit accesses for 32-bit fields, etc), but the +used (i.e. 32-bit accesses for 32-bit fields, etc), but +when accessed through the legacy interface the device-specific region can be accessed using any width accesses, and should obtain the same results. Note that this is possible because while the virtio header is PCI -(i.e. little) endian, the device-specific region is encoded in -the native endian of the guest (where such distinction is +(i.e. little) endian, when using the legacy interface the device-specific +region is encoded in the native endian of the guest (where such distinction is applicable). 2.3.1.2.1. PCI Device Virtio Header -- MST